In an integrated circuit chip, such as a dynamic random access memory (“DRAM”) chip, a clock signal is used as a reference signal for adjusting operational timing in the circuit. When an external clock signal enters into a circuit, the clock phase of internal clock signals based on the external clock signal may be delayed because of the inherent delay of the components of the circuit. The clock phase may be adjusted to match the phase of the external clock using a delay circuit such as a delay locked loop (“DLL”). However, the use of delay circuits can distort the clock signal, creating a signal with a duty cycle that departs from the ideal 50% duty cycle.
The size of circuit elements continues to decrease with each successive generation of semiconductor memory devices, and the speed of such devices continues to increase. At such increased operating speeds, distortions in the clock signal duty cycle may adversely affect the functioning of the circuit. Traditional DLL's may include a single phase mixer that receives two input signals (e.g., clock signals) offset by some phase difference and provide a single output signal having a phase that is a mix of the phases of the two input signals. This process of combining clock signals to generate a single output signal having a phase based on the two input signals may be referred to as phase mixing or phase interpolating. In order to adjust the delay of the output signal, the phase mixer may receive one or more control signals for weighting the phases of the input signals so that the output signal is a weighted combination of the phases of the input signals. The weighting may be adjusted to provide an output signal having a desired phase. However, conventional phase mixers may cause duty cycle deviation and provide a duty cycle distorted output clock signal. As previously discussed, distortions in the clock signal duty cycle may adversely affect the functioning of the circuit.